HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 41

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 12.8
Figure 12.9
Figure 12.10 Inverted Pulse Output (Example)......................................................................... 624
Figure 12.11 Pulse Output Triggered by Input Capture (Example) .......................................... 625
Section 13 8-Bit Timers (TMR)
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Figure 13.10 Contention between TCNT Write and Clear........................................................ 643
Figure 13.11 Contention between TCNT Write and Increment ................................................ 644
Figure 13.12 Contention between TCOR Write and Compare Match ...................................... 645
Section 14 Watchdog Timer
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Figure 15.8
Figure 15.9
Setup Procedure for Non-Overlapping Pulse Output (Example) ......................... 621
Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............ 622
Block Diagram of 8-Bit Timer Module ............................................................... 628
Example of Pulse Output ..................................................................................... 637
Count Timing for Internal Clock Input ................................................................ 637
Count Timing for External Clock Input ............................................................... 638
Timing of CMF Setting........................................................................................ 638
Timing of Timer Output....................................................................................... 639
Timing of Compare Match Clear ......................................................................... 639
Timing of Clearance by External Reset ............................................................... 640
Timing of OVF Setting ........................................................................................ 640
Block Diagram of WDT....................................................................................... 650
Operation in Watchdog Timer Mode ................................................................... 655
Operation in Interval Timer Mode ....................................................................... 656
Contention between TCNT Write and Increment ................................................ 658
Circuit for System Reset by WDTOVF Signal (Example) .................................. 659
Block Diagram of SCI ......................................................................................... 663
Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. 691
Receive Data Sampling Timing in Asynchronous Mode..................................... 693
Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) ......................................................................................... 694
Sample SCI Initialization Flowchart.................................................................... 695
Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 696
Sample Serial Transmission Flowchart................................................................ 697
Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 698
Sample Serial Reception Data Flowchart (1)....................................................... 700
Writing to TCNT, TCSR, and RSTCSR ............................................................. 657
Rev. 3.00 Mar 17, 2006 page xxxix of l