HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 225

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.6
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.6.1
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.4
Note:
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
6.6.2
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.5 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
RMTS2
0
1
* Reserved (setting prohibited) in the H8S/2678 Group.
DRAM Interface
Setting DRAM Space
Address Multiplexing
RMTS1
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
0
1
0
1
RMTS0
1
0
1
0
1
0
1
Normal space Normal space Normal space
Normal space Normal space
DRAM space
Continuous
DRAM space
Area 5
Mode register settings of synchronous DRAM *
Continuous synchronous DRAM space *
DRAM space
Reserved (setting prohibited)
Continuous
DRAM space
Area 4
Rev. 3.00 Mar 17, 2006 page 173 of 926
Section 6 Bus Controller (BSC)
DRAM space
DRAM space
Continuous
DRAM space
Area 3
REJ09B0283-0300
DRAM space
DRAM space
DRAM space
Continuous
DRAM space
Area 2