HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 403

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller
In block transfer mode, a transfer of the specified block size is executed in response to one transfer
request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be
performed at the same high speed as in block transfer mode.
When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the
transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be
performed endlessly.
Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged,
can be specified independently for each address register.
In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of
bytes.
8.4.2
Address Modes
Dual Address Mode: In dual address mode, both the transfer source and transfer destination are
specified by registers in the EXDMAC, and one transfer is executed in two bus cycles.
The transfer source address is set in the source address register (EDSAR), and the transfer
destination address is set in the transfer destination address register (EDDAR).
In a transfer operation, the value in external memory specified by the transfer source address is
read in the first bus cycle, and is written to the external memory specified by the transfer
destination address in the next bus cycle.
These consecutive read and write cycles are indivisible: another bus cycle (external access by an
internal bus master, refresh cycle, or external bus release cycle) does not occur between these two
cycles.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for two consecutive bus cycles. The EDACK signal is not output.
Figure 8.2 shows an example of the timing in dual address mode.
Rev. 3.00 Mar 17, 2006 page 351 of 926
REJ09B0283-0300