HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 227

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.6.4
Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5
pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5
signals are output.
Table 6.6
Pin
HWR
CS2
CS3
CS4
CS5
UCAS
LCAS
RD, OE
WAIT
A15 to A0
D15 to D0
Pins Used for DRAM Interface
DRAM Interface Pins
With DRAM
Setting
WE
RAS2/RAS
RAS3
RAS4
RAS5
UCAS
LCAS
OE
WAIT
A15 to A0
D15 to D0
Name
Write enable
Row address strobe 2/
row address strobe
Row address strobe 3
Row address strobe 4
Row address strobe 5
Upper column address
strobe
Lower column address
strobe
Output enable
Wait
Address pins
Data pins
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
I/O
Rev. 3.00 Mar 17, 2006 page 175 of 926
Function
Write enable for DRAM space
access
Row address strobe when area
2 is designated as DRAM space
or row address strobe when
areas 2 to 5 are designated as
continuous DRAM space
Row address strobe when area
3 is designated as DRAM space
Row address strobe when area
4 is designated as DRAM space
Row address strobe when area
5 is designated as DRAM space
Upper column address strobe
for 16-bit DRAM space access
or column address strobe for 8-
bit DRAM space access
Lower column address strobe
signal for 16-bit DRAM space
access
Output enable signal for DRAM
space access
Wait request signal
Row address/column address
multiplexed output
Data input/output pins
Section 6 Bus Controller (BSC)
REJ09B0283-0300