HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 20

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.4
7.5
7.6
7.7
Section 8 EXDMA Controller
8.1
8.2
8.3
Rev. 3.00 Mar 17, 2006 page xviii of l
7.3.7
Activation Sources ............................................................................................................ 286
7.4.1
7.4.2
7.4.3
Operation .......................................................................................................................... 288
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMA Bus Cycles (Single Address Mode) ........................................................... 318
7.5.11 Write Data Buffer Function ................................................................................. 324
7.5.12 Multi-Channel Operation ..................................................................................... 325
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,
7.5.14 DMAC and NMI Interrupts.................................................................................. 327
7.5.15 Forced Termination of DMAC Operation............................................................ 327
7.5.16 Clearing Full Address Mode ................................................................................ 328
Interrupt Sources............................................................................................................... 329
Usage Notes ...................................................................................................................... 330
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
Features ............................................................................................................................. 335
Input/Output Pins .............................................................................................................. 337
Register Descriptions ........................................................................................................ 338
8.3.1
8.3.2
8.3.3
DMA Terminal Control Register (DMATCR)..................................................... 285
Activation by Internal Interrupt Request.............................................................. 287
Activation by External Request ........................................................................... 287
Activation by Auto-Request................................................................................. 288
Transfer Modes .................................................................................................... 288
Sequential Mode .................................................................................................. 290
Idle Mode............................................................................................................. 292
Repeat Mode ........................................................................................................ 295
Single Address Mode........................................................................................... 298
Normal Mode....................................................................................................... 301
Block Transfer Mode ........................................................................................... 304
Basic Bus Cycles.................................................................................................. 309
DMA Bus Cycles (Dual Address Mode) ............................................................. 310
and EXDMAC ..................................................................................................... 326
DMAC Register Access during Operation........................................................... 330
Module Stop......................................................................................................... 331
Write Data Buffer Function ................................................................................. 331
TEND Output....................................................................................................... 332
Activation by Falling Edge on DREQ Pin ........................................................... 333
Activation Source Acceptance ............................................................................. 334
Internal Interrupt after End of Transfer................................................................ 334
Channel Re-Setting .............................................................................................. 334
EXDMA Source Address Register (EDSAR) ...................................................... 338
EXDMA Destination Address Register (EDDAR) .............................................. 339
EXDMA Transfer Count Register (EDTCR)....................................................... 339
......................................................................................... 335