HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 418

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller
IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an interrupt request source occurs.
If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested.
The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer
ends following the end of the DMA transfer bus cycle in which the source generating the interrupt
occurred.
If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared.
For details on interrupts, see section 8.5, Interrupts Sources.
8.4.8
The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3.
Table 8.3 shows the EXDMAC channel priority order.
Table 8.3
Channel
Channel 0
Channel 1
Channel 2
Channel 3
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order in table 8.3 is selected for transfer.
Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode): If
transfer requests for different channels are issued during a transfer operation, the highest-priority
channel (excluding the currently transferring channel) is selected. The selected channel begins
transfer after the currently transferring channel releases the bus. If there is a bus request from a bus
mastership other than the EXDMAC at this time, a cycle for the other bus mastership is initiated.
If there is no other bus request, the bus is released for one cycle.
Channels are not switched during burst transfer or transfer of a block in block transfer mode.
Figure 8.13 shows an example of the transfer timing when transfer requests occur simultaneously
for channels 0, 1, and 2. The example in the figure is for external request cycle steal mode.
Rev. 3.00 Mar 17, 2006 page 366 of 926
REJ09B0283-0300
Channel Priority Order
EXDMAC Channel Priority Order
Priority
High
Low