HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 868

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 21 Clock Pulse Generator
Table 21.3 External Clock Input Conditions
21.3
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR.
The phase of the rising edge of the internal clock is controlled so as to match that of the rising
edge of the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR.
For details on SBYCR, refer to section 22.1.1, Standby Control Register (SBYCR).
1. The initial PLL circuit multiplication factor is 1.
Rev. 3.00 Mar 17, 2006 page 816 of 926
REJ09B0283-0300
Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
PLL Circuit
EXTAL
t
EXr
Figure 21.5 External Clock Input Timing
Symbol
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
t
EXH
V
Min
15
15
—
—
0.4
0.4
CC
= 3.0 V to 3.6 V
Max
—
—
5
5
0.6
0.6
t
EXf
t
EXL
Unit
ns
ns
ns
ns
t
t
cyc
cyc
V
CC
Test Conditions
Figure 21.5
0.5