HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 37

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 7.29
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Figure 7.33
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Figure 7.41
Section 8 EXDMA Controller
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Figure 8.12
Figure 8.13
Figure 8.14
Figure 8.15
Figure 8.16
Figure 8.17
Figure 8.18
Figure 8.19
Figure 8.20
Figure 8.21
Figure 8.22
Example of Single Address Mode Transfer (Word Write) .................................. 321
Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer 322
Example of DREQ Pin Low Level Activated Single Address Mode Transfer .... 323
Example of Dual Address Transfer Using Write Data Buffer Function .............. 324
Example of Single Address Transfer Using Write Data Buffer Function............ 325
Example of Multi-Channel Transfer .................................................................... 326
Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt.................................................................................................. 327
Example of Procedure for Forcibly Terminating DMAC Operation ................... 328
Example of Procedure for Clearing Full Address Mode...................................... 328
Block Diagram of Transfer End/Transfer Break Interrupt................................... 329
DMAC Register Update Timing .......................................................................... 330
Contention between DMAC Register Update and CPU Read ............................. 331
Example in Which Low Level Is Not Output at TEND Pin................................. 333
Block Diagram of EXDMAC .............................................................................. 336
Example of Timing in Dual Address Mode ......................................................... 352
Data Flow in Single Address Mode ..................................................................... 353
Example of Timing in Single Address Mode....................................................... 354
Example of Timing in Cycle Steal Mode............................................................. 356
Examples of Timing in Burst Mode..................................................................... 357
Examples of Timing in Normal Transfer Mode................................................... 358
Example of Timing in Block Transfer Mode....................................................... 359
Example of Repeat Area Function Operation ...................................................... 360
Example of Repeat Area Function Operation in Block Transfer Mode............... 361
EDTCR Update Operations in Normal Transfer Mode
and Block Transfer Mode .................................................................................... 364
Procedure for Changing Register Settings in Operating Channel ........................ 365
Example of Channel Priority Timing................................................................... 367
Examples of Channel Priority Timing ................................................................. 368
Example of Normal Transfer Mode (Cycle Steal Mode) Transfer....................... 369
Example of Normal Transfer Mode (Burst Mode) Transfer ................................ 370
Example of Block Transfer Mode (Cycle Steal Mode) Transfer ......................... 371
Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge...... 372
Example of Block Transfer Mode Transfer Activated by EDREQ Pin
Falling Edge......................................................................................................... 373
Example of Normal Mode Transfer Activated by EDREQ Pin Low Level......... 374
Example of Block Transfer Mode Transfer Activated by EDREQ Pin
Low Level ............................................................................................................ 375
Example of Single Address Mode (Byte Read) Transfer..................................... 376
Rev. 3.00 Mar 17, 2006 page xxxv of l