HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 169

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC’s DMABCR, the DTCE bit of DTC’s DTCERA to DTCERH, and the
DISEL bit of DTC’s MRB.
Table 5.6
Legend:
Note: The SCI or A/D converter interrupt source is cleared when the DMAC or DTC reads or
5.7
5.7.1
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
DMAC
DTA
0
1
X : The relevant interrupt cannot be used.
* : Don’t care
: The relevant interrupt is used. Interrupt source clearing is performed.
: The relevant interrupt is used. The interrupt source is not cleared.
(The CPU should clear the source flag in the interrupt handling routine.)
writes to the prescribed register, and is not dependent upon the DTA bit or DISEL bit.
Usage Notes
Contention between Interrupt Generation and Disabling
Interrupt Source Selection and Clearing Control
DTCE
0
1
*
Settings
DTC
DISEL
*
0
1
*
Interrupt Sources Selection/Clearing Control
DMAC
Rev. 3.00 Mar 17, 2006 page 117 of 926
DTC
X
X
Section 5 Interrupt Controller
REJ09B0283-0300
CPU
X
X