HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 451

IC H8S MCU FLASH 256K 144-QFP

HD64F2676VFC33

Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2676VFC33

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2676VFC33
Manufacturer:
RENESAS
Quantity:
5 530
Part Number:
HD64F2676VFC33
Quantity:
9 520
Part Number:
HD64F2676VFC33
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F2676VFC33V
Manufacturer:
RENESAS
Quantity:
5 530
Part Number:
HD64F2676VFC33V
Manufacturer:
ROHM
Quantity:
750 000
Part Number:
HD64F2676VFC33V
Manufacturer:
RENESAS
Quantity:
120
Part Number:
HD64F2676VFC33V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
8.6.4
At the start of activation source acceptance, low level sensing is used for both falling edge sensing
and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low
level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transfer-
enabled state.
When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the
EDREQ pin from the previous end of transfer, etc.
8.6.5
When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in
EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be
requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request
when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1.
8.6.6
If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that
although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may
also go low in this case for the refresh cycle.
Activation Source Acceptance
Enabling Interrupt Requests when IRF = 1 in EDMDR
ETEND Pin and CBR Refresh Cycle
ETEND
ETEND
ETEND
Rev. 3.00 Mar 17, 2006 page 399 of 926
Section 8 EXDMA Controller
REJ09B0283-0300

Related parts for HD64F2676VFC33