HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 168

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
(1) Selection of Interrupt Source: The activation factors for each channel of DMAC are selected
by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the
selected activation factors are managed by DMAC. By setting the DTA bit to 1, the interrupt
factor which were the activation factor for that DMAC do not act as the DTC activation factor or
the CPU interrupt factor.
Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation
source or CPU interrupt source by the DTCE bit of DTCERA to DTCERF of DTC.
By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.
If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, and an interrupt is requested to the CPU.
(2) Determination of Priority: The DTC activation source is selected in accordance with the
default priority order, and is not affected by mask or priority levels. See table 9.1 for the respective
priority. DMAC inputs activation factor directly to each channel.
Rev. 3.00 Mar 17, 2006 page 116 of 926
REJ09B0283-0300
supporting
On-chip
interrupt
module
IRQ
Interrupt source
clear signal
Interrupt
request
Figure 5.6 DTC, DMAC, and Interrupt Controller
Interrupt controller
Selection
DTVECR
DTCER
circuit
Select
signal
clear signal
Clear signal
SWDTE
DMAC
Determination of
Control logic
priority
DTC activation
request vector
number
CPU interrupt
request vector
number
Clear signal
I, I2 to I0
DTC
CPU