HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 309
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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temporary release of the bus in the event of an external access request from an internal bus master.
For details see section 8, EXDMA Controller.
External Bus Release: When the BREQ pin goes low and an external bus release request is issued
while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
6.13
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.14
6.14.1
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of
the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the
all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus
controller and I/O ports. In this state, the external bus release function is halted. To use the
external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0.
Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is
executed in the external bus released state, the transition to all-module-clocks-stopped mode is
deferred and performed until after the bus is recovered.
6.14.2
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
Bus Controller Operation in Reset
Usage Notes
External Bus Release Function and All-Module-Clocks-Stopped Mode
External Bus Release Function and Software Standby
Rev. 3.00 Mar 17, 2006 page 257 of 926
Section 6 Bus Controller (BSC)
REJ09B0283-0300
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