HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 39

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 8.45
Figure 8.46
Section 9 Data Transfer Controller (DTC)
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Figure 9.12
Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
Figure 11.10 Example of Synchronous Operation Setting Procedure ....................................... 565
Figure 11.11 Example of Synchronous Operation .................................................................... 566
Figure 11.12 Compare Match Buffer Operation ....................................................................... 567
Figure 11.13 Input Capture Buffer Operation ........................................................................... 567
Figure 11.14 Example of Buffer Operation Setting Procedure ................................................. 568
Figure 11.15 Example of Buffer Operation (1) ......................................................................... 569
Figure 11.16 Example of Buffer Operation (2) ......................................................................... 570
Figure 11.17 Cascaded Operation Setting Procedure................................................................ 571
Figure 11.18 Example of Cascaded Operation (1) .................................................................... 571
Figure 11.19 Example of Cascaded Operation (2) .................................................................... 572
Figure 11.20 Example of PWM Mode Setting Procedure......................................................... 574
Figure 11.21 Example of PWM Mode Operation (1)................................................................ 575
Transfer End Interrupt Logic ............................................................................... 395
Example of Procedure for Restarting Transfer on Channel in which Transfer
End Interrupt Occurred ........................................................................................ 397
Block Diagram of DTC........................................................................................ 402
Block Diagram of DTC Activation Source Control............................................. 407
Correspondence between DTC Vector Address and Register Information.......... 408
Flowchart of DTC Operation ............................................................................... 411
Memory Mapping in Normal Mode..................................................................... 413
Memory Mapping in Repeat Mode...................................................................... 414
Memory Mapping in Block Transfer Mode ......................................................... 415
Operation of Chain Transfer ................................................................................ 416
DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................ 417
DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) ........................................................................................... 417
DTC Operation Timing (Example of Chain Transfer)......................................... 418
Chain Transfer when Counter = 0........................................................................ 424
Block Diagram of TPU ........................................................................................ 524
Example of Counter Operation Setting Procedure............................................... 559
Free-Running Counter Operation......................................................................... 560
Periodic Counter Operation ................................................................................. 561
Example of Setting Procedure for Waveform Output by Compare Match .......... 561
Example of 0 Output/1 Output Operation............................................................ 562
Example of Toggle Output Operation.................................................................. 562
Example of Setting Procedure for Input Capture Operation ................................ 563
Example of Input Capture Operation ................................................................... 564
Rev. 3.00 Mar 17, 2006 page xxxvii of l