HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 841

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.6.1
When this LSI enters boot mode, the embedded boot program is started. The boot program
transfers the programming control program from the externally connected host to the on-chip
RAM via the SCI_1. When the flash memory is all erased, the programming control program is
executed.
Table 19.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip
2. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the end of
3. When boot mode is used, the flash memory programming control program must be prepared in
4. Before branching to the programming control program, the chip terminates transfer operations
5. In boot mode, if flash memory contains data (all data is not 1), all blocks of flash memory are
measures the low-level period of asynchronous SCI communication data (H'00) transmitted
continuously from the host. The chip then calculates the bit rate of transmission from the host,
and adjusts the SCI_1 bit rate to match that of the host. The transfer format is 8-bit data, 1 stop
bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should
be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states
before the chip is ready to measure the low-level period.
bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has
been received normally, and transmit one H'55 byte to the chip. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 19.6.
the host beforehand. Prepare a programming control program in accordance with the
description in section 19.8, Flash Memory Programming/Erasing.
by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
program data or verify data with the host. The TxD pin is high. The contents of the CPU
general registers are undefined immediately after branching to the programming control
program. These registers must be initialized at the beginning of the programming control
program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
erased. Boot mode is used for the initial programming in the on-board state or for a forcible
Boot Mode
Section 19 Flash Memory (F-ZTAT Version)
Rev. 3.00 Mar 17, 2006 page 789 of 926
REJ09B0283-0300