HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 445

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller
8.4.12
Ending DMA Transfer
The operation for ending DMA transfer depends on the transfer end conditions. When DMA
transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has
ended.
Transfer End by 1
0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0,
DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If
the TCEIE bit in EDMDR is set at this time, a transfer end interrupt request is generated by the
transfer counter and the IRF bit in EDMDR is set to 1.
In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes
from 1 to 0.
DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer.
Transfer End by Repeat Area Overflow Interrupt: If an address overflows the repeat area
when a repeat area specification has been made and repeat interrupts have been enabled (with the
SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer
ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit in EDMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
Transfer End by 0-Write to EDA Bit in EDMDR: When 0 is written to the EDA bit in EDMDR
by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress
or a transfer request was accepted.
In block transfer mode, DMA transfer halts after completion of one-block-size transfer.
The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that
point, the value of the EDA bit will be read as 1.
Transfer Abort by NMI Interrupt: DMA transfer is aborted when an NMI interrupt is
generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is
performed for all transfer requests for which EDRAK has been output. In dual address mode,
processing is executed for the write cycle following the read cycle.
Rev. 3.00 Mar 17, 2006 page 393 of 926
REJ09B0283-0300