EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1014

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–56
Table 1–18. MegaWizard Plug-In Manager Options (SONET/SDH Screen) (Part 2 of 3)
Stratix IV Device Handbook Volume 3
What is the word alignment
pattern?
Flip word alignment pattern bits.
What do you want the byte
ordering to be based on?
Enable run-length violation
checking with a run length of.
Create an rx_syncstatus output
port for pattern detector and word
aligner.
Create an rx_patterndetect
port to indicate pattern detected.
ALTGX Setting
Enter the word alignment pattern. By default, the
pattern that appears in the MegaWizard Plug-In
Manager is '0001010001101111' (16'h146F).
This option is enabled in the MegaWizard Plug-In
Manager by default. This option reverses the order
of the alignment pattern at a bit level to support
MSB-to-LSB transmission in SONET/SDH mode.
The ALTGX MegaWizard Plug-In Manager flips the
bit order of the default word alignment pattern
'0001010001101111 '(16'h146F) and uses the
flipped version '1111011000101000' (16'hF628) as
the word alignment pattern.
This option allows you to trigger the byte ordering
block either on the rising edge of the
rx_syncstatus signal or the user-controlled
rx_enabyteord signal from the FPGA fabric. The
byte ordering block is enabled only in OC-48 mode.
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s and
0s exceeds the number that you set in this option,
the run-length violation circuit asserts the rx_rlv
signal. The rx_rlv signal is asynchronous to the
receiver data path and is asserted for a minimum of
two recovered clock cycles in OC-12 and OC-48
modes. Similarly, it is asserted for a minimum of
three recovered clock cycles in the OC-96 mode.
For the OC-12 and OC-48 modes, the run length
limits are 4 to 128 in increments of four. For the
OC-96 mode, the run length limits are 5 to 160 in
increments of five.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that
synchronization has been achieved. This signal is
synchronous with the parallel receiver data on the
rx_dataout port. The signal width is 1 bit, 2 bits,
and 4 bits for a channel width of 8 bits, 16 bits, and
32 bits, respectively.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. The signal width is 1 bit,
2 bits, and 4 bits for a channel width of 8 bits,
16 bits, and 32 bits, respectively.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the
Stratix IV Devices
“Byte Ordering Block” section
in the
in Stratix IV Devices
“Programmable Run Length
Violation Detection” section in
the
Stratix IV Devices
Table 1-77 and “Word Aligner”
section in the
Architecture in Stratix IV
Devices
Table 1-33 and “Word Aligner”
section in the
Architecture in Stratix IV
Devices
February 2011 Altera Corporation
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture
chapter.
chapter.
Reference
Transceiver
Transceiver
—
Protocol Settings
chapter.
chapter.
chapter.