EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 597
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–121. XAUI and XGMII Layers
February 2011 Altera Corporation
Presentation
Model Layers
Application
Transport
Data Link
Reference
Network
Physical
Session
OSI
XAUI Mode
XAUI is an optional, self-managed interface that you can insert between the
reconciliation sublayer and the PHY layer to transparently extend the physical reach
of the XGMII.
XAUI addresses several physical limitations of the XGMII. XGMII signaling is based
on the HSTL Class 1 single-ended I/O standard, which has an electrical distance
limitation of approximately 7 cm. Because XAUI uses a low-voltage differential
signaling method, the electrical limitation is increased to approximately 50 cm.
Another advantage of XAUI is simplification of backplane and board trace routing.
XGMII is composed of 32 transmit channels, 32 receive channels, 1 transmit clock,
1 receive clock, 4 transmitter control characters, and 4 receive control characters for a
74-pin wide interface. XAUI, on the other hand, only consists of 4 differential
transmitter channels and 4 differential receiver channels for a 16-pin wide interface.
This reduction in pin count significantly simplifies the routing process in the layout
design.
Figure 1–121
shows the relationships between the XGMII and XAUI layers.
Optional
XGMII
Extender
Access/Collision Detect (CSMA/CD)
Media Access Control (MAC)
Logical Link Control (LLC)
LAN Carrier Sense Multiple
XGMII Extender Sublayer
XGMII Extender Sublayer
MAC Control (Optional)
Higher Layers
Reconciliation
Medium
10 Gb/s
Layers
PCS
PMA
PMD
Stratix IV Device Handbook Volume 2: Transceivers
Physical Layer Device
10 Gigabit Media Independent Interface
10 Gigabit Attachment Unit Interface
10 Gigabit Media Independent Interface
Medium Dependent Interface
1–153
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