EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 596

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–152
Stratix IV Device Handbook Volume 2: Transceivers
f
f
1
Table 1–57
configured using the Fast Passive Parallel (FPP) configuration scheme at 125 MHz.
Table 1–57. Typical Configuration Times for Stratix IV GX Devices Configured with Fast Passive
Parallel
For more information about the FPP configuration scheme, refer to the
Design Security, Remote System Upgrades in Stratix IV Devices
Most flash memories available can run up to 100 MHz. To configure the
Stratix IV GX and GT device at 125 MHz, Altera recommends using a MAX II device
to convert the 16-bit flash memory output at 62.5 MHz to 8-bit configuration data
input to the Stratix IV GX and GT device at 125 MHz.
The PCI Express Electrical Gold Test requires the v2.0 CBB to be connected to the
Device Under Test (DUT). The CBB sends out a 100 MHz signal for 1 ms to indicate
the Link Training and Status State Machine (LTSSM) of the downstream device Under
Test (DUT) to transition to several polling compliance states. Under these states, the
DUT sends out data at Gen1, Gen2 (with -3.5db de-emphasis), and Gen2 (with -6 db
de-emphasis) rates, which can be observed in the scope to confirm electrical signal
compliance. The CBB is DC-coupled to the downstream receiver.
When you use the Stratix IV GX and GT device as DUT, because of being DC-coupled
to CBB with a different common mode level, the Stratix IV GX and GT receiver does
not receive the required V
that implements LTSSM cannot transition to the multiple polling compliance states to
complete the test. Therefore, when testing with the CBB, force the LTSSM
implemented in the FPGA fabric to transfer to different polling compliance states
using an external push button or user logic.
If you use the Stratix IV GX and GT PCIe hard IP block, assert the test_in[6] port of
the PCIe Compiler-generated wrapper file in your design. Asserting this port forces
the LTSSM within the hard IP block to transition to these states. The test_in[6] port
must be asserted for a minimum of 16 ns and less than 24 ms.
For more information about the PCIe hard IP block, refer to the
User
PCI Express Electrical Gold Test with Compliance Base Board (CBB)
Guide.
Stratix IV GX
EP4SGX110
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4SGX70
lists the typical configuration times for Stratix IV GX devices when
CM
(0.85 V) to detect the signal. The logic in the FPGA fabric
EP4S(40/100)G2
EP4S(40/100)G5
Stratix IV GT
EP4S100G3
EP4S100G4
Chapter 1: Transceiver Architecture in Stratix IV Devices
—
—
chapter.
February 2011 Altera Corporation
Configuration Time (ms)
PCI Express Compiler
Transceiver Block Architecture
128
128
172
48
48
95
Configuration,