EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 999

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 3 of 4)
February 2011 Altera Corporation
Flip word alignment pattern
bits.
Enable run-length violation
checking with a run length of:
Enable word aligner output
reverse bit ordering.
Create an rx_syncstatus
output port for pattern
detector and word aligner.
Create an
rx_patterndetect port to
indicate pattern detected.
ALTGX Setting
When this option is enabled, the ALTGX MegaWizard
Plug-In Manager flips the bit order of the pattern that
you enter in the What is the word alignment pattern?
option and uses the flipped version as the word
alignment pattern. For example, if you enter
'0101111100' (17C) as the word alignment pattern
and enable this option, the word aligner uses
'0011111010' as the word alignment pattern.
This option creates the output signal rx_rlv. Enabling
this option also activates the run-length violation
circuit. If the number of continuous 1s and 0s exceeds
the number that you set in this option, the run-length
violation circuit asserts the rx_rlv signal. The
rx_rlv signal is asynchronous to the receiver data
path and is asserted for a minimum of two recovered
clock cycles in Single-width mode. Similarly, it is
asserted for a minimum of three recovered clock
cycles in Double-width mode.
The run length limits are as follows:
■
■
In manual bit-slip mode, this option creates an input
port rx_revbitorderwa to dynamically reverse the
bit order at the output of the receiver word aligner.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that
synchronization has been achieved. This signal is
synchronous with the parallel receiver data on the
rx_dataout port. This signal is not available in
bit-slip mode. Signal width is 1, 2, and 4 bits for a
channel width of 8-bits/10-bits, 16-bits/20-bits, and
32-bits/40-bits, respectively.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. Signal width is 1, 2, and 4
bits for a channel width of 8-bits/10-bits,
16-bits/20-bits, and 32-bits/40-bits, respectively.
Single-width mode:
■
■
Double-width mode:
■
■
8-bit and 16-bit channel width: 4 to 128 in
increments of four
10-bit and 20-bit channel width: 5 to 160 in
increments of five
16-bit and 32-bit channel width: 8 to 512 in
increments of eight
20-bit and 40-bit channel width: 10 to 640 in
increments of 10
Description
“Programmable Run Length
Violation Detection” section in the
Transceiver Architecture in
Stratix IV Devices
“Receiver Bit Reversal” section in
the
Stratix IV Devices
Table 1-77, “Word Aligner in
Single-Width Mode” and “Word
Aligner in Double-Width Mode”
sections in the
Architecture in Stratix IV Devices
chapter.
Table 1-77 and “Word Aligner in
Single-Width Mode” and “Word
Aligner in Double-Width Mode”
sections in the
Architecture in Stratix IV Devices
chapter.
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Reference
Transceiver
Transceiver
—
chapter.
chapter.
1–41