EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 532

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–88
Figure 1–74. Rate Match FIFO Full Condition in Basic Double-Width Mode
Figure 1–75. Rate Match FIFO Empty Condition in Basic Double-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions.
The rate match FIFO in Basic double-width mode automatically deletes the pair of
data byte that causes the FIFO to go full and asserts the rx_rmfifofull flag
synchronous to the subsequent pair of data bytes.
Figure 1–74
The rate match FIFO becomes full after receiving the 20-bit word D5D6.
The rate match FIFO automatically inserts a pair of /K30.7/ ({9'h1FE,9'h1FE}) after the
data byte that causes the FIFO to go empty and asserts the rx_fifoempty flag
synchronous to the inserted pair of /K30.7/ ({9'h1FE,9'h1FE}).
Figure 1–75
The rate match FIFO becomes empty after reading out the 20-bit word D5D6.
rx_rmfifoempty
dataout[19:0]
dataout[19:0]
datain[19:10]
datain[19:10]
dataout[9:0]
dataout[9:0]
datain[9:0]
datain[9:0]
rx_rmfifofull
shows the rate match FIFO full condition in Basic double-width mode.
shows the rate match FIFO empty condition in Basic double-width mode.
D2
D1
D2
D1
D2
D1
D2
D1
D4
D3
D4
D3
D4
D3
D4
D3
D6
D5
D6
D5
D6
D5
D6
D5
/K30.7/
/K30.7/
D8
D7
D10
D9
D8
D7
Chapter 1: Transceiver Architecture in Stratix IV Devices
D10
D12
D11
D9
D10
D9
D8
D7
D11
D12
xx
xx
D12
D11
D10
D9
February 2011 Altera Corporation
Transceiver Block Architecture