EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 688
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
2–16
Figure 2–10. Legal FPGA Fabric-Transceiver PLL Cascading Configuration
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 0
Channel 2
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 3
Channel 0
Channel 0
Channel 3
Channel 2
Channel 1
Channel 1
ATX PLL L1 (6G)
ATX PLL L0 (6G)
CMU1
CMU1
CMU0
CMU0
CMU1
CMU1
CMU0
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Case 2: use PLL_R1 to provide the input reference clock to the receiver CDRs in
channel 2 and channel 3 (shown in BLUE) and use PLL_R4 to provide the input
reference clock to the CMU0 PLL (shown in GREEN) in transceiver block GXBR1.
Figure 2–10
legal as there is no crossover of the cascade clock paths on the PLL cascade network.
Cascade
Network
PLL
shows that this FPGA fabric-Transceiver PLL cascading configuration is
PLL_L3
PLL_L2
PLL_L4
PLL_L1
EP4SGX530NF45
PLL_R3
PLL_R2
PLL_R1
PLL_R4
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
Cascade
Network
PLL
February 2011 Altera Corporation
Transceiver Block GXBR0
Transceiver Block GXBR2
Transceiver Block GXBR2
Transceiver Block GXBR1
ATX PLL R1 (6G)
ATX PLL R0 (6G)
CMU1
CMU1
CMU1
CMU1
CDR
CMU0
CDR
CMU0
CDR
CMU0
CDR
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Channel 2
Channel 2
Channel 1
Channel 0
Channel 3
Channel 1
Channel 0
Channel 3
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 0
Channel 1
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