EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 770

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–16
Combining Transceiver Instances Using PLL Cascade Clocks
Stratix IV Device Handbook Volume 2: Transceivers
f
1
For inst1, the ALTGX MegaWizard Plug-In Manager provides a pll_inclk port. In
this example, it is assumed that a single reference clock is provided for inst0 and
inst1. Therefore, connect the pll_inclk port of inst0 and inst1 to the same input
reference clock pin. This enables the Quartus II software to share a single CMU PLL in
transceiver block 1 that has three channels of inst0 and one channel of inst1 (shown
as ch4, ch5, and ch6 in transceiver block 1 in
For the RX CDRs in inst0, the ALTGX MegaWizard Plug-In Manager provides seven
bits for the rx_cruclk port (if you do not select the Train Receiver CDR from
pll_inclk option in the PLL/Ports screen). This allows separate input reference clocks
to the RX CDRs of each channel.
The Stratix IV GX and GT transceiver has the ability to cascade the output of the
general purpose PLLs (PLL_L and PLL_R) to the CMU PLLs, ATX PLLs, and receiver
CDRs. The left side PLLs can only be cascaded with the transceivers on the left side of
the device. Similarly, the right side PLLs can only be cascaded with the transceivers on
the right side of the device. Each side of the Stratix IV GX and GT device contains a
PLL cascade clock network; a single line network that connects the PLL cascade clock
to the transceiver block. This clock line is segmented to allow different PLL cascade
clocks to drive the transceiver CMU PLLs, ATX PLLs, and RX CDRs. Within the same
segment, only a single PLL_L/PLL_R can drive these transceiver PLLs/CDRs.
Therefore, if you create two instances that use different PLLs for cascading, you
cannot place these instances within the transceiver block.
The segmentation locations differ based on the device family.
For more information about using the PLL cascade clock and segmentation, refer to
the “Dedicated Left and Right PLL Cascade Lines Network” section in the
Clocking in Stratix IV Devices
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
chapter.
Combining Transceiver Instances Using PLL Cascade Clocks
Figure
3–6).
February 2011 Altera Corporation
Transceiver