EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 451

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Channel Locations
February 2011 Altera Corporation
Figure 1–4
EP4SGX530 Stratix IV GX device that has 24 and 36 transceiver channels and the
remaining Stratix IV GX devices that have 48 transceiver channels.
Figure 1–4. Transceiver Channel, PLL, and PCIe Hard IP Block Locations with 48 Stratix IV GX
Transceiver Channels and EP4SGX530 with 24, 36, and 48 Stratix IV GX Transceiver Channels
Notes to
(1) The 6G ATX PLL R1 and L1 blocks are not available in the EP4SGX530KF40 devices.
(2) Only the EP4SGX530 device in the six transceiver block package has four PCI hard IP blocks.
Figure
shows transceiver channel, PLL, and PCIe hard IP block locations in each
1–4:
EP4SGX290NF45, EP4SGX360NF45, EP4SGX530NF45
EP4SGX530KF43,
EP4SGX530KF40
(1),
Transceiver Block GXBL2
Transceiver Block GXBL2
Transceiver Block GXBL0
(2) (36 transceivers)
Transceiver Block GXBL1
ATX PLL L1 (6G) (1)
EP4SGX530HH35
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL L0 (6G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
(24 transceivers)
(48 transceivers)
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
Transceiver Block GXBR2
ATX PLL R1 (6G) (1)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL R01 (6G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 1
Channel 0
Channel 3
Channel 2
Channel 3
Channel 2
Channel 1
Channel 0
1–7