EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 682
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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20 000
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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2–10
Stratix IV Device Handbook Volume 2: Transceivers
Dedicated Left and Right PLL Cascade Network
Stratix IV devices have a dedicated PLL cascade network on the left and right side of
the device that connects to the input reference clock selection multiplexer of the
CMU PLLs, 6G ATX PLLs, and receiver CDRs on the left and right side of the device,
respectively.
The dedicated PLL cascade networks are segmented by bidirectional tri-state buffers
located along the clock line. Segmentation of the dedicated PLL cascade network
allows two or more left and right PLLs to drive the cascade clock line simultaneously.
Because the number of left and right PLLs and transceiver blocks vary from device to
device, the capability of cascading a left and right PLL to the CMU PLLs, 6G ATX
PLLs, and receiver CDRs also varies from device to device.
The following sections describe the Stratix IV GX and GT FPGA fabric-Transceiver
PLLs cascading for the various device packages.
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
February 2011 Altera Corporation
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