EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 637
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–157. Reverse Serial Loopback Datapath (Grayed-Out Blocks are Not Active in this Mode)
February 2011 Altera Corporation
Fabric
FPGA
RX Phase
Compen-
sation
FIFO
Reverse Serial Loopback
Reverse serial loopback is available as a subprotocol under Basic functional mode. In
reverse serial loopback mode, the data is received through the rx_datain port,
retimed through the receiver CDR and sent out to the tx_dataout port. The received
data is also available to the FPGA logic. No dynamic pin control is available to select
or deselect reverse serial loopback.
datapath for reverse serial loopback mode.
The active block of the transmitter channel is only the transmitter buffer. You can
change the output differential voltage and the pre-emphasis first post tap values on
the transmitter buffer through the ALTGX MegaWizard Plug-In Manager or through
the dynamic reconfiguration controller. Reverse serial loopback is often implemented
when using a bit error rate tester (BERT) on the upstream transmitter.
TX Phase
Compen-
Ordering
sation
FIFO
Byte
Serialzier
De-Serializer
Byte
Byte
Encoder
8B/10B
8B/10B
Decoder
Figure 1–157
Transmitter Channel PCS
Receiver Channel PCS
shows the transceiver channel
Aligner
Stratix IV Device Handbook Volume 2: Transceivers
Word
Loopback
Reverse
Serializer
Serial
Transmitter Channel PMA
Receiver Channel PMA
De-
Serializer
Receiver
CDR
1–193
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