EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 975

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Figure 1–5. MegaWizard Plug-In Manager—ALTGX (Ports/Calibration Screen)
Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 1 of 3)
February 2011 Altera Corporation
Optional Ports/Controls
Create an rx_signaldetect port to
indicate data input signal detection.
Enable TX Phase Comp FIFO in register
mode.
Create an
rx_phase_comp_fifo_error output
port.
Ports/Calibration Screen for the Parameter Settings
ALTGX Setting
Figure 1–5
Manager for the Parameter Settings.
Table 1–3
MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
Unless indicated otherwise, the options apply to all functional modes.
lists the available options on the Ports/Calibration screen of the
shows the Ports/Calibration screen of the ALTGX MegaWizard Plug-In
This port is only available in Basic
and PCIe mode.
This option is only available in
Deterministic Latency mode.
This output port indicates a Receiver
Phase Compensation FIFO overflow
or under-run condition.
Description
“Signal Threshold Detection Circuitry”
section in the
Stratix IV Devices
“Deterministic Latency” section in the
Transceiver Architecture in Stratix IV
Devices
“Receiver Phase Compensation FIFO Error
Flag” section in the
Architecture in Stratix IV Devices
chapter.
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Reference
chapter.
Transceiver
chapter.
1–17