EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 642
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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1–198
Figure 1–163. Location of Transceiver Channel and PLL in Stratix IV GT Devices (EP4S40G2F40, EP4S40G5H40,
EP4S100G2F40 and EP4S100G5H40)
Figure 1–164. Location of Transceiver Channel and PLL in Stratix IV GT Devices (EP4S100G5F45)
Stratix IV Device Handbook Volume 2: Transceivers
Input Reference Clocks for the ATX PLL Block
Figure 1–163
each Stratix IV GT device.
The 6G ATX PLL block does not have a dedicated reference clock pin. The following
are the possible input reference clock sources:
■
■
■
Altera recommends using the REFCLK pins from the adjacent transceiver block below
the ATX PLL block to improve performance.
REFCLKs from the transceiver blocks on the same side of the device if the
corresponding CMU channels are not used as transceiver channels
Input reference clock provided through the PLL cascade clock network
Clock inputs connected through the global clock lines
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Transceiver Block GXBL2
Transceiver Block GXBL3
Transceiver Block GXBL1
Transceiver Block GXBL0
ATX PLL L1 (10G)
ATX PLL L0 (6G)
ATX PLL L2 (10G)
ATX PLL L1 (6G)
ATX PLL L0 (6G)
and
Figure 1–164
show the locations of the 6G and 10G ATX PLLs in
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
Transceiver Block GXBR1
Chapter 1: Transceiver Architecture in Stratix IV Devices
ATX PLL R2 (10G)
ATX PLL R1 (6G)
ATX PLL R0 (6G)
ATX PLL R1 (10G)
ATX PLL R0 (6G)
Auxiliary Transmit (ATX) PLL Block
February 2011 Altera Corporation
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