EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 365

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
Figure 10–13. PS Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(2) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA[0] is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings.
Table 10–7. PS Timing Parameters for Stratix IV Devices (Part 1 of 2)
April 2011 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
f
t
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
R
Symbol
When nCONFIG is pulled low, a reconfiguration cycle begins.
Figure
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Input rise time
10–13:
CONF_DONE (3)
nSTATUS (2)
INIT_DONE
nCONFIG
User I/O
PS Configuration Timing
Figure 10–13
device as an external host.
Table 10–7
DCLK
DATA
(5)
(5)
(5)
t
t
CFG
CF2CD
t
CF2ST1
t
lists the timing parameters for Stratix IV devices for PS configuration.
Parameter
CF2ST0
t
CF2CK
t
ST2CK
shows the timing waveform for PS configuration when using a MAX II
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
(Note 1)
Bit n
(Note 1)
Minimum
500
3.2
3.2
—
—
10
—
—
—
2
2
4
0
8
t
CD2UM
Stratix IV Device Handbook Volume 1
Maximum
500
500
User Mode
800
800
125
—
—
—
—
—
—
—
—
40
(5)
(4)
(2)
(3)
Units
MHz
ns
ns
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
10–31