EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 121
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Figure 5–3. RCLK Networks (EP4S40G2, EP4S100G2, EP4SGX180, and EP4SGX230 Devices)
Note to
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
Figure 5–4. RCLK Networks (EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530, EP4SE820,
EP4SGX290, EP4SGX360, and EP4SGX530 Devices)
Notes to
(1) The corner RCLK[64..87] can only be fed by their respective corner PLL outputs. For more information about connectivity, refer to
(2) The EP4S40G5 and EP4SE360 devices have up to eight PLLs. For more information about PLL availability, refer to
(3) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
February 2011 Altera Corporation
another four core signals can drive into RCLK[54..63] at any one time.
page
another four core signals can drive into RCLK[54..63] at any one time.
Figure
Figure
5–13.
5–3:
5–4:
CLK[0..3]
CLK[0..3]
L2
L3
L1
L2
L3
L4
RCLK[82..87]
RCLK[64..69]
RCLK[6..11]
RCLK[0..5]
RCLK[0..5]
RCLK[6..11]
RCLK[12..21] RCLK[22..31]
RCLK[54..63] RCLK[44..53]
RCLK[54..63] RCLK[44..53]
RCLK[12..21] RCLK[22..31]
(Note
CLK[12..15]
CLK[12..15]
CLK[4..7]
Q1
Q4
CLK[4..7]
Q1 Q2
Q4 Q3
T1
B1
T1
B1
1), (2),
T2
B2
T2
B2
Q2
Q3
(3)
RCLK[38..43]
RCLK[32..37]
RCLK[76..81]
RCLK[32..37]
RCLK[70..75]
RCLK[38..43]
R2
R3
R1
R2
R3
R4
CLK[8..11]
CLK[8..11]
Stratix IV Device Handbook Volume 1
(Note 1)
Table 5–7 on page
Table 5–6 on
5–19.
5–5
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