EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 751
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
Table 2–20. Quartus II Assignments for Appendix Example 4
February 2011 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) This is an example design hierarchy path for the rx_clkout[9] signal.
Table
Configuration Example 4: Configuring Left and Right, Left, or Right PLL in
VCO Bypass Mode
2–20:
1
Table 2–20
scheme shown in
This example relates to
page
To configure the left and right, left, or right PLL in VCO bypass mode, follow these
steps:
1. Under the General/Modes tab, enter the desired input reference clock frequency.
Figure 2–41. No Compensation Option Used for Configuration Example 4
top_level/top_xcvr_instance1/altgx_component/rx_clkout[9]
rx_datain[15..0]
GXB 0 PPM Core Clock Setting
ON
a. Under PLL Type, select Left_Right_PLL.
b. Under Operation mode, select the With no compensation option
2–17.
(Figure
lists the Quartus II assignments that you must make for the clocking
2–41).
Figure
“Left and Right, Left, or Right PLL in VCO Bypass Mode” on
2–40.
Stratix IV Device Handbook Volume 2: Transceivers
(1)
2–79
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