EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 665

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 2 of 4)
February 2011 Altera Corporation
tx_pipemargin
tx_pipedeemph
pipe8b10binvpolarity
Port Name
Output
Input/
Input
Input
Input
Clock Domain
Asynchronous
Asynchronous
Asynchronous
signal
signal
signal
Transmitter differential output voltage level control.
Transmitter buffer de-emphasis level control.
PCIe polarity inversion control.
Functionally equivalent to the txmargin signal
defined in the PCIe specification revision 2.0.
Available only in PCIe Gen2 configuration.
The width of this signal is 3 bits and is decoded
as follows:
Functionally equivalent to the txdeemph signal
defined in the PCIe specification revision 2.0.
Available only in PCIe Gen2 configuration.
1’b0: -6 dB de-emphasis
1’b1:-3.5 dB de-emphasis
Functionally equivalent to the rxpolarity
signal defined in the PCIe specification revision
2.0.
Available only in PCIe mode.
When asserted high—the polarity of every bit of
the 10-bit input data to the 8B/10B decoder gets
inverted.
3’b000—Normal Operating Range
3’b001—Full Swing = 800 - 1200 mV
3’b010—TBD
3’b011—TBD
3’b100—If last value, full Swing = 200 to 400
mV
3’b101—If last value, full Swing = 200 to 400
mV
3’b110—If last value, full Swing = 200 to 400
mV
3’b111—If last value, full Swing = 200 to 400
mV
Stratix IV Device Handbook Volume 2: Transceivers
Description
1–221
Channel
Scope

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