EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 117

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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SIV51005-3.2
Clock Networks in Stratix IV Devices
Table 5–1. Clock Resources in Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
February 2011
February 2011
SIV51005-3.2
SIV51005-3.2
Clock input pins
GCLK networks
RCLK networks
PCLK networks
GCLKs/RCLKs per
quadrant
Clock Resource
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
which have advanced features in Stratix
ability to reconfigure the PLL counter clock frequency and phase shift in real time,
allowing you to sweep PLL output frequencies and dynamically adjust the output
clock phase shift.
The Quartus
devices. The following sections describe the Stratix IV clock networks and PLLs in
detail:
■
■
The global clock networks (GCLKs), regional clock networks (RCLKs), and periphery
clock networks (PCLKs) available in Stratix IV devices are organized into hierarchical
clock structures that provide up to 236 unique clock domains (16 GCLKs + 88 RCLKs
+ 132 PCLKs) within the Stratix IV device and allow up to 71 unique GCLK, RCLK,
and PCLK clock sources (16 GCLKs + 22 RCLKs + 33 PCLKs) per device quadrant.
Table 5–1
Number of Resources Available
56/88/112/132 (33 per device
“Clock Networks in Stratix IV Devices” on page 5–1
“PLLs in Stratix IV Devices” on page 5–19
32 Single-ended
(16 Differential)
quadrant)
lists the clock resources available in Stratix IV devices.
64/88
32/38
®
II software enables the PLLs and their features without external
16
(1)
(3)
(2)
5. Clock Networks and PLLs in Stratix IV
DPA clock outputs, PLD-transceiver interface clocks, horizontal
CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and
CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and
®
IV devices. It includes details about the
CLK[0..15]p and CLK[0..15]n pins
Source of Clock Resource
I/O pins, and logic array
16 GCLKs + 16 RCLKs
16 GCLKs + 22 RCLKs
logic array
logic array
Devices
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