EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 314

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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8–36
Stratix IV Device Handbook Volume 1
2.
Figure 8–29. Input Time Delay Assignment Through TimeQuest Timing Analyzer
3.
Figure 8–30. Name Finder Window in Set Input Delay Option
Figure 8–29
clock name must reference the source synchronous clock that feeds the LVDS
receiver. Select the desired clock using the pull-down menu.
Figure 8–30
using the List option in the Name Finder window.
shows the setting parameters for the Set Input Delay option. The
shows the Targets option. You can view a list of all available ports
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
February 2011 Altera Corporation

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