EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 674

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–2
Glossary of Terms
Table 2–1. Glossary of Terms Used in this chapter
Input Reference Clocking
Stratix IV Device Handbook Volume 2: Transceivers
ATX PLL
CDR
CMU
ITB lines
Convention
Table 2–1
Each transceiver block has:
■
■
Auxiliary transmit PLL block. For more information, refer to the “Auxiliary Transmit (ATX) PLL
Block” section in the
Clock data recovery block. For more information, refer to the “Clock and Data Recovery Unit”
section in the
Clock multiplier unit. For more information, refer to “CMU Channel Architecture” section in the
Transceiver Architecture in Stratix IV Devices
The Inter-Transceiver block (ITB) clock lines provide an input reference clock path from the
refclk pins of one transceiver block CMU PLLs and receiver CDRs of other transceiver blocks.
They also provide input reference clock to ATX PLLs. For more information, refer to
Transceiver Block (ITB) Clock Lines” on page
Two clock multiplier unit channels—the CMU0_Channel and CMU1_Channel
You can configure each as either a CMU to generate transceiver clocks or as a
PMA-Only channel.
f
Four regular channels
When the CMU channel is configured as a CMU, the CMU PLL synthesizes the
input reference clock to generate the high-speed serial transceiver clock. When the
CMU channel is configured as a Receiver Only or Receiver and Transmitter
channel, the CMU PLL acts as a CDR and uses the input reference clock as a
training clock when it is in lock-to-reference (LTR) mode. Each of the four regular
channels also has a receiver CDR that uses the input reference clock as a training
clock when it is in LTR mode.
Each Stratix IV device also has ATX PLLs that you can use in addition to the CMU
PLLs to generate the high-speed serial transceiver clock. The ATX PLLs also need
an input reference clock for operation. 6G ATX PLLs are available in both
Stratix IV GX and Stratix IV GT devices. 10G ATX PLLs are available only in
Stratix IV GT devices.
f
lists the terms used in the chapter.
For more information, refer to the “CMU Channel Architecture” section in
the
For more information, refer to the “Auxiliary Transmit (ATX) PLL Block”
and the “Transmitter Channel Datapath” sections in the
Architecture in Stratix IV Devices
Transceiver Architecture in Stratix IV Devices
Transceiver Architecture in Stratix IV Devices
Transceiver Architecture in Stratix IV Devices
Description
chapter.
2–8.
chapter.
Chapter 2: Transceiver Clocking in Stratix IV Devices
chapter.
chapter.
chapter.
February 2011 Altera Corporation
Transceiver
Glossary of Terms
“Inter-