EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 561

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–98. Transceiver Configurations in Basic Double-Width Mode with a 16-Bit PMA-PCS Interface for Stratix IV GX
Devices
Notes to
(1) The maximum data rate specification shown in
(2) The byte ordering block is available only if you select the word alignment pattern length of 16 or 32 bits.
February 2011 Altera Corporation
other speed grades offered, refer to the
Figure
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
(1)
(1)
Interface Clock Cycles)
1–98:
TX PCS Latency
Interface Frequency
RX PCS Latency
Interface Frequency
Fabric-Transceiver
Interface Frequency
Fabric-Transceiver
Low-Latency PCS
Data Rate (Gbps)
Encoder/Decoder
Data Rate (Gbps)
Rate Match FIFO
(Pattern Length)
Channel Bonding
Interface Width
Interface Width
FPGA Fabric -
Byte Ordering
Interface Width
Word Aligner
Transceiver
Byte SerDes
PMA-PCS
PMA-PCS
FPGA
(MHz)
Functional
8B/10B
FPGA
Modes
Basic Double-Width Mode Configurations
Figure 1–98
double-width functional mode with a 16-bit PMA-PCS interface.
Figure 1–99
double-width functional mode with a 16-bit PMA-PCS interface.
8-Bit
Disabled
Disabled
11 - 13
DC and Switching Characteristics
Single-
Width
16-Bit
shows Stratix IV GX transceiver configurations allowed in Basic
shows Stratix IV GT transceiver configurations allowed in Basic
62.5 -
5 - 6
1.0 -
250
4.0
Manual Alignment
10-Bit
(8-, 16-, 32-Bit)
Disabled
Disabled
Figure 1–98
Basic
6.5 - 8.5
Disabled
203.125
31.25 -
4 - 5.5
16-Bit
32-Bit
Enabled
Double-
Width
1.0 -
6.5
Disabled
6.5 - 8.5
20-Bit
Enabled
203.125
31.25 -
4 - 5.5
32-Bit
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Stratix IV GX Configurations
(2)
Disabled
10-Bit
PIPE
Disabled
11 - 13
16-Bit
62.5 -
5 - 6
1.0 -
4.0
250
(8-, 16-, 32-Bit)
chapter.
Disabled
Disabled
Bit-Slip
10-Bit
XAUI
Basic Double-Width
16-Bit PMA-PCS
Interface Width
Enabled
6.5 - 8.5
Disabled
203.125
1.0 - 8.5
31.25 -
4 - 5.5
32-Bit
1.0 -
x1, x4, x8
6.5
GIGE
10-Bit
Protocol
SRIO
10-Bit
Stratix IV Device Handbook Volume 2: Transceivers
SONET
/SDH
8-Bit
16-Bit
(OIF)
CEI
10-Bit
SDI
Disabled
Disabled
16-Bit
62.5 -
3 - 4
1.0 -
4 - 5
250
4.0
Disabled
Disabled
Disabled
Enabled
10-Bit
Deterministic
Latency
Disabled
Enabled
265.625
31.25 -
4 - 5.5
3 - 4.5
32-Bit
1.0 -
8.5
20-Bit
1–117