EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 580
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H40I3
Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
Quantity:
1 200
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 580 of 1154
- Download datasheet (32Mb)
1–136
Table 1–49. Power State Functions and Descriptions
Figure 1–113. Power State Transition from the P0 to P2 Power State
Stratix IV Device Handbook Volume 2: Transceivers
Power State
P0s
P0
P1
P2
pipephydonestatus
1
powerdn[1:0]
powerdn
Parallel
2’b00
2’b01
2’b10
2’b11
Clock
The PCIe specification provides the mapping of these power states to the LTSSM
states specified in the PCIe Base Specification 2.0. The PHY-MAC layer is responsible
for implementing the mapping logic between the LTSSM states and the four power
states in the PCIe-compliant PHY.
The PCIe interface in Stratix IV GX and GT transceivers provides an input port,
powerdn[1:0], for each transceiver channel configured in PCIe mode.
mapping between the logic levels driven on the powerdn[1:0] port and the resulting
power state that the PCIe interface block puts the transceiver channel into.
When transitioning from the P0 power state to lower power states (P0s, P1, and P2),
the PCIe specification requires the physical layer device to implement power saving
measures. Stratix IV GX and GT transceivers do not implement these power saving
measures except putting the transmitter buffer in electrical idle in the lower power
states.
The PCIe interface block indicates successful power state transition by asserting the
pipephydonestatus signal for one parallel clock cycle as specified in the PCIe
specification. The PHY-MAC layer must not request any further power state
transition until the pipephydonestatus signal has indicated the completion of the
current power state transition request.
Figure 1–113
state.
Transmits normal data, transmits electrical idle, or
enters into loopback mode
Only transmits electrical idle
Transmitter buffer is powered down and can do a
receiver detect while in this state
Transmits electrical idle or a beacon to wake up the
downstream receiver
2'b00 (P0)
shows an example waveform for a transition from the P0 to P2 power
Function
2'b11 (P2)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Normal operation mode
Low recovery time saving state
High recovery time power saving
state
Lowest power saving state
February 2011 Altera Corporation
Description
Transceiver Block Architecture
Table 1–49
lists
Related parts for EP4SE530H40I3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: