EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 287

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
ALTLVDS Port List
ALTLVDS Port List
Table 8–7. Port List of the LVDS Interface (ALTLVDS)
February 2011 Altera Corporation
PLL Signals
pll_areset
LVDS Transmitter Interface Signals
tx_in[ ]
tx_inclock
tx_enable
tx_out
tx_outclock
tx_coreclock
tx_locked
Port Name
(3)
(3)
Table 8–7
lists the interface signals for an LVDS transmitter and receiver.
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input /
Asynchronous reset to the LVDS transmitter and receiver PLL. The
minimum pulse width requirement for this signal is 10 ns.
The data bus width per channel is the same as the serialization factor (SF).
Input data must be synchronous to the tx_coreclock signal.
Reference clock input for the transmitter PLL.
The ALTLVDS MegaWizard Plug-In Manager software automatically selects
the appropriate PLL multiplication factor based on the data rate and
reference clock frequency selection.
For more information about the allowed frequency range for this reference
clock, refer to the “High-Speed I/O Specification” section in the
Switching Characteristics for Stratix IV Devices
This port is instantiated only when you select the Use External PLL option
in the MegaWizard Plug-In Manager software. This input port must be
driven by the PLL instantiated though the ALTPLL MegaWizard Plug-In
Manager software.
LVDS transmitter serial data output port. tx_out is clocked by a serial clock
generated by the left and right PLL.
The frequency of this clock is programmable to be the same as the data
rate, half the data rate, or one-fourth the data rate. The phase offset of this
clock, with respect to the serial data, is programmable in increments of 45°.
FPGA fabric-transmitter interface clock. The parallel transmitter data
generated in the FPGA fabric must be clocked with this clock.
This port is not available when you select the Use External PLL option in the
MegaWizard Plug-In Manager software. The FPGA fabric-transmitter
interface clock must be driven by the PLL instantiated through the ALTPLL
MegaWizard Plug-In Manager software.
When high, this signal indicates that the transmitter PLL is locked to the
input reference clock.
(Note
1),
(2)
(Part 1 of 3)
Description
Stratix IV Device Handbook Volume 1
chapter.
DC and
8–9