EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 914

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–68
Figure 5–35. Dynamic Reconfiguration Signals Transition during Offset Cancellation on Receiver Channels
Note to
(1) After device power up, the busy signal remains low for the first reconfig_clk cycle.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
EyeQ
5–35:
f
1
1
reconfig_clk
Figure 5–35
cancellation on the receiver channels.
Due to the offset cancellation process, the transceiver reset sequence has changed. For
more information, refer to the
chapter.
EyeQ hardware is available in Stratix IV transceivers to analyze and debug the
receiver data recovery path (receiver gain, clock jitter, and noise level). You can use it
to monitor the eye width and assess the quality of the incoming signal.
Normally, the receiver CDR samples the incoming signal at the center of the eye.
When you enable the EyeQ hardware, it allows the CDR to sample across 32 different
positions across one unit interval (UI) of the incoming data. You can manually control
the sampling points and check the bit-error rate (BER) at each of these 32 sampling
points. These sampling points are also known as phase steps.
The BER increases at the edge of the eye-opening. By observing the number of
sampling points results in a desired BER value, you can determine the eye width.
The EyeQ hardware is available for both regular transceiver channels and CMU
channels.
For more information about the supported data rates, phase step translation, and
other specifications, refer to the
chapter.
busy
(1)
shows the dynamic reconfiguration signals transition during offset
Reset Control and Power Down in Stratix IV Devices
DC and Switching Characterization for Stratix IV Devices
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation