EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 880
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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5–34
Stratix IV Device Handbook Volume 2: Transceivers
■
■
Consider the following scenario:
■
■
■
■
Option 2 is applicable because the design requires the individual transceiver channels
to be reconfigured with different data rates to another Basic or Protocol functional
mode with rate matching. Therefore, each channel can be reconfigured to another
Basic or Protocol functional mode with rate matching enabled and a different data
rate.
Enable this option if you want the individual transmitter channel’s tx_clkout
signal to provide the read clock to its respective Receive Phase Compensation
FIFO.
This option is typically enabled when all the transceiver channels have rate
matching enabled with different data rates and are reconfigured to another Basic
or Protocol functional mode with rate matching enabled.
TX0/RX0: You want to dynamically reconfigure the Basic 1 Gbps configuration
with rate matching enabled to the Basic 2 Gbps configuration with rate matching
enabled.
TX1/RX1: You want to dynamically reconfigure the Basic 4 Gbps configuration
with rate matching enabled to the Basic 1 Gbps configuration with rate matching
enabled.
TX2/RX2 and TX3/RX3: You want to dynamically reconfigure the Basic
3.125 Gbps configuration with rate matching enabled to the 1 Gbps configuration
with rate matching and vice versa.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
Option 2: Use the Respective Channel Transmitter Core Clocks
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
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