EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 644

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–200
Figure 1–166. ATX Clock Divider
Table 1–70. Differences Between the 10G ATX PLL, 6G ATX PLL, and CMU PLL (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
Available in
Data rates (Gbps)
Input reference clock
options
PCIE_gen2switch_done
Difference Category/PLLs
clock output
high-speed
ATX PLL
PCIE_gen2switch
The Differences Between 10G ATX PLL, 6G ATX PLL, and CMU PLL
f
ATX Clock Divider
The ATX clock divider divides the ATX PLL high-speed clock and provides
high-speed serial and low-speed parallel clock for bonded functional modes such as
PCIe (×4 and ×8), Basic ×4 and ×8, and PMA-Direct mode with ×N configuration. For
PCIe functional mode support, the ATX clock divider consists of the PCIe rateswitch
circuit to enable dynamic rateswitch between PCIe Gen1 and Gen2 data rates. For
more information on this circuit, refer to
The clock outputs from the ATX PLL block are provided to the transmitter channels
through the ×N_Top or ×N_bottom clock lines, as shown in
For more information, refer to the
Table 1–70
PLL.
pins on the same side of
Only dedicated refclk
Stratix IV GT device
the device (2),
lists the differences between the 10G ATX PLL, 6G ATX PLL, and CMU
10G ATX PLL
9.9 to 11.3
ATX clock divider block
clockswitch circuit
(3)
PCIe
■
■
■
1.2 to 1.35 and 1.5 to 1.625
2.4 to 2.7 and 3.0 and 3.25
Stratix IV GX and GT devices
Clock inputs connected
through the inter transceiver
block (ITB) lines.
Clock inputs connected
through the PLL cascade clock
network.
Clock inputs connected
through the global clock lines.
(3)
Transceiver Clocking for Stratix IV Devices
4.8 to 5.4 and 6.0 and 6.5
0
1
6G ATX PLL
“CMU0 Channel” on page
Chapter 1: Transceiver Architecture in Stratix IV Devices
(4, 5, 8, 10)
/S
(1)
(1)
/2
Figure
Auxiliary Transmit (ATX) PLL Block
February 2011 Altera Corporation
■
■
■
■
■
Stratix IV GX and GT devices
Up to 8.5 for Stratix IV GX
devices
Up to 11.3 for
Stratix IV GT devices
Clock inputs connected
through the inter
transceiver block (ITB)
lines.
clock inputs connected
through the PLL cascade
clock network.
Clock inputs connected
through the global clock
lines, refclk0 and
refclk1 clock input,
dedicated refclks in the
transceiver block.
1–166.
coreclkout to FPGA fabric
1–101.
(for bonded modes)
(for bonded modes)
CMU PLL
(for bonded modes)
High-Speed
Serial Clock
Parallel Clocks
Low-Speed
chapter.
(3)