DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 3

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

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9
10 ELECTRICAL CHARACTERISTICS ................................................................................................................... 97
11 PIN ASSIGNMENTS ......................................................................................................................................... 104
12 MECHANICAL INFORMATION ........................................................................................................................ 106
13 ACRONYMS AND ABBREVIATIONS............................................................................................................... 108
14 DATA SHEET REVISION HISTORY ................................................................................................................ 109
7.8
7.9
7.10 Microprocessor Interface ........................................................................................................................... 41
7.11 Reset Logic................................................................................................................................................ 43
7.12 Power-Supply Considerations ................................................................................................................... 43
7.13 Initialization................................................................................................................................................ 43
REGISTER DESCRIPTIONS.............................................................................................................................. 44
8.1
8.2
8.3
8.4
JTAG TEST ACCESS PORT AND BOUNDARY SCAN..................................................................................... 93
9.1
9.2
9.3
9.4
10.1 DC Characteristics..................................................................................................................................... 97
10.2 Input Clock Timing................................................................................................................................... 100
10.3 Output Clock Timing ................................................................................................................................ 100
10.4 SPI Interface Timing ................................................................................................................................ 101
10.5 JTAG Interface Timing............................................................................................................................. 102
10.6 Reset Pin Timing ..................................................................................................................................... 103
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Output Clock Configuration ....................................................................................................................... 31
Frame and Multiframe Alignment .............................................................................................................. 38
Status Bits ................................................................................................................................................. 44
Configuration Fields................................................................................................................................... 44
Multi-Register Fields.................................................................................................................................. 44
Register Definitions ................................................................................................................................... 45
JTAG Description ...................................................................................................................................... 93
JTAG TAP Controller State Machine Description ..................................................................................... 93
JTAG Instruction Register and Instructions............................................................................................... 95
JTAG Test Registers ................................................................................................................................. 96
7.8.1
7.8.2
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
7.9.7
7.9.8
Signal Format Configuration......................................................................................................... 31
Frequency Configuration .............................................................................................................. 31
Sampling....................................................................................................................................... 38
Resampling................................................................................................................................... 39
Enable .......................................................................................................................................... 39
Qualification.................................................................................................................................. 39
Output Clock Alignment................................................................................................................ 39
Frame Sync Monitor ..................................................................................................................... 39
SYNCn Pins.................................................................................................................................. 40
Other Configuration Options......................................................................................................... 40
Preliminary. Subject to Change Without Notice.
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DS3105