DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 17

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Table 7-1. Input Clock Capabilities
Note 1:
Note 2:
7.4.2
Input clock frequencies are configured in the FREQ field of the
same registers specify the locking frequency mode, as shown in
Table 7-2. Locking Frequency Modes
7.4.2.1
In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the corresponding
register. Direct lock mode can only be used for input clocks with these specific frequencies: 2 kHz, 4 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 5 MHz, 6.312 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 31.25 MHz, 38.88 MHz, 51.84
MHz, 77.76 MHz and 155.52 MHz. For the 155.52 MHz case, the input clock is internally divided by two, and the
DPLL direct-locks at 77.76 MHz. The DIVN mode can be used to divide an input down to any of these frequencies
except 155.52 MHz.
MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent
phase updates.
7.4.2.2
Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used
(see the FREQ field definition in the
clock rates found in Ethernet, CMTS, wireless and GPS applications. The alternate frequencies are: 10 MHz, 25
MHz, 62.5 MHz, 125 MHz and 156.25 MHz. The frequencies 62.5 MHz, 125 MHz and 156.25 MHz are internally
divided down to 31.25 MHz, while 10 MHz and 25 MHz are internally divided down to 5 MHz.
7.4.2.3
In LOCK8K mode, an internal divider is configured to divide the selected reference down to 8 kHz. The DPLL locks
to the 8 kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock
frequencies: 8 kHz, 1.544 MHz, 2.048 MHz, 5 MHz, 6.312 MHz, 6.48 MHz, 19.44 MHz, 25.0 MHz, 25.92 MHz,
31.25 MHz, 38.88 MHz, 51.84 MHz, 62.5 MHz, 77.76 MHz and 155.52 MHz. LOCK8K mode is enabled for a
particular input clock by setting the LOCK8K bit in the corresponding
LOCK8K mode gives a greater tolerance to input jitter when the multi-cycle phase detector is disabled because it
uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
Input Clock
DIVN
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0
0
1
1
IC3
IC4
IC5
IC6
IC9
Available frequencies for CMOS/TTL input clocks are: 2 kHz, 4 kHz, 8 kHz, 1.544 MHz (SONET mode), 2.048 MHz (SDH mode),
6.312 MHz, 6.48 MHz, 19.44 MHz, 25.0 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 62.5 MHz, 77.76 MHz, and any multiple of 2 kHz
up to 125MHz.
Available frequencies for LVDS/LVPECL input clocks include all CMOS/TTL frequencies in Note 1 plus any multiple of 8 kHz up to
155.52 MHz and 156.25 MHz.
Frequency Configuration
Direct Lock Mode
Alternate Direct Lock Mode
LOCK8K Mode
LOCK8K
LVDS / LVPECL
LVDS / LVPECL
Signal Formats
0
1
0
1
or CMOS/TTL
or CMOS/TTL
CMOS / TTL
CMOS / TTL
CMOS / TTL
Locking Frequency Mode
Direct Lock mode
LOCK8K mode
DIVN mode
Alternate Direct Lock mode
Frequencies
up to 125 MHz
up to 125 MHz
up to 156.25 MHz
up to 156.25 MHz
up to 125 MHz
Preliminary. Subject to Change Without Notice.
ICR
register description). The alternate frequencies are included to support
(1)
(1)
(1)
(2)
(2)
17 of 110
ICR
Default Frequency
8 kHz
8 kHz
19.44 MHz
19.44 MHz
19.44 MHz
Table
registers. The DIVN and LOCK8K bits of these
ICR
7-2.
register.
DS3105
ICR