DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 18

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

configured using the 8KPOL bit in the
direct-lock mode is used.
7.4.2.4
In DIVN mode, an internal divider is configured from the value stored in the
be chosen so that when the selected reference is divided by DIVN+1, the resulting clock frequency is the same as
the standard direct lock frequency selected in the FREQ field of the
the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 155.52 MHz.
The DIVN register field can range from 0 to 65,535 inclusive. The same DIVN+1 factor is used for all input clocks
configured for DIVN mode. Note that although the DIVN divider is able to divide down clock rates as high as 155.52
MHz, the CMOS/TTL inputs are only rated for a maximum clock rate of 125 MHz.
7.5 Input Clock Monitoring
Each input clock is continuously monitored for activity. Activity monitoring is described in sections
The valid/invalid state of each input clock is reported in the corresponding real-time status bit in registers
or VALSR2. When the valid/invalid state of a clock changes, the corresponding latched status bit is set in registers
MSR1
IER2. Input clocks marked invalid cannot be automatically selected as the reference for either DPLL.
7.5.1
The DS3105 monitors the frequency of each input clock and invalidates any clock whose frequency is more than
10,000 ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN bit.
The frequency range measurement uses the internal 204.8 MHz master clock as the frequency reference.
7.5.2
Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket
accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and
gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully
between events and no alarm is declared. When events occur close enough together, the accumulator increments
faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events
occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the
alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.
The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 through 3) in the
BUCKET field of the
threshold, alarm clear threshold, and decay rate, all of which are specified in the
Activity monitoring is divided into 128-ms intervals. The accumulator is incremented once for each 128ms interval
in which the input clock is inactive for more than two cycles (more than four cycles for 155.52 MHz, 156.25 MHz,
125 MHz, 62.5 MHz, 25 MHz and 10 MHz input clocks). Thus the “fill” rate of the bucket is at most 1 unit per 128
ms, or approximately 8 units/second. During each period of 1, 2, 4 or 8 intervals (programmable), the accumulator
decrements if no irregularities occur. Thus the “leak” rate of the bucket is approximately 8, 4, 2 or 1 units/second. A
leak is prevented when a fill event occurs in the same interval.
When the value of an accumulator reaches the alarm threshold
set to 1 in the
accumulator reaches the alarm clear threshold
ACT bit. The accumulator cannot increment past the size of the bucket specified in the
rate of the accumulator is specified in the
registers must have the following relationship at all times:
When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the
‘x’ in ‘LBxU’ is the leaky bucket configuration number, 0 to 3). The minimum time to clear an activity alarm in
seconds is 2^LBxD * (LBxS – LBxL) / 8. As an example, assume LBxU = 8, LBxL = 1, LBxS = 10 and LBxD = 0.
The minimum time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity
alarm would be 2^0 * (10 – 1) / 8 = 1.125 seconds.
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or MSR2, and an interrupt request occurs if the corresponding interrupt enable bit is set in registers
Frequency Monitoring
Activity Monitoring
DIVN Mode
ISR
registers, and the clock is marked invalid in the
ICR
registers. Each leaky bucket configuration has programmable size, alarm declare
Preliminary. Subject to Change Without Notice.
TEST1
LBxD
register. For 2 kHz and 4 kHz clocks the LOCK8K bit is ignored and
(LBxL
register. The values stored in the leaky bucket configuration
18 of 110
register), the activity alarm is cleared by clearing the clock’s
LBxS
(LBxU
>=
LBxU
ICR
register), the corresponding ACT alarm bit is
VALSR
> LBxL.
register. The DPLL locks to the output of
DIVN
LBxy
registers. When the value of an
registers. The DIVN value must
registers.
LBxS
register. The decay
7.5.2
and 7.5.3.
VALSR1
DS3105
IER1
or