DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 83

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the T4 phase detector 2 is enabled and
the gain is determined by the input locking frequency. If the frequency is greater than 8 kHz, the gain is set by the
PD2G field. If the frequency is less or equal to 8 kHz, the gain is set by the PD2G8K field in the
See section 7.7.5.
Bits 2 to 0: Phase Detector 2 Gain (PD2G[2:0]). This field specifies the gain of the T4 phase detector 2 when the
input frequency is greater than 8 kHz. This value is only used if automatic gain selection is enabled by setting
PD2EN=1. See section 7.7.5.
Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the T0 phase detector 2 is enabled and
the gain is determined by the input locking frequency. If the frequency is greater than 8 kHz, the gain is set by the
PD2G field. If the frequency is less or equal to 8 kHz, the gain is set by the PD2G8K field in the
See section 7.7.5.
Bits 2 to 0: Phase Detector 2 Gain (PD2G[2:0]). This field specifies the gain of the T0 phase detector 2 when the
input frequency is greater than 8 kHz. This value is only used if automatic gain selection is enabled by setting
PD2EN=1. See section 7.7.5.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = Disable
1 = Enable
0 = Disable
1 = Enable
PD2EN
PD2EN
Bit 7
Bit 7
1
1
Bit 6
Bit 6
1
1
T4CR3
T4 Configuration Register 3
6Ch
T0CR3
T0 Configuration Register 3
6Dh
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
0
0
--
--
83 of 110
Bit 4
Bit 4
0
0
Bit 3
Bit 3
0
0
Bit 2
Bit 2
0
0
PD2G[2:0]
PD2G[2:0]
Bit 1
Bit 1
1
1
T4CR2
T0CR2
Bit 0
Bit 0
DS3105
register
register
0
0