DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 55

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 5 to 2: Input Clock Valid Status (IC6 to IC3). Each of these real-time status bits is set to 1 when the
corresponding input clock is valid. An input is valid if it has no active alarms (HARD = 0, ACT = 0, LOCK = 0 in the
corresponding
Register Name:
Register Description:
Register Address:
Name
Default
Bit 6: Holdover Frequency Ready (HORDY). This real-time status bit is set to 1 when the T0 DPLL has a
holdover value that has been averaged over the 1-second holdover averaging period. See the related latched
status bit in
Bit 0: Input Clock Valid Status (IC9). This bit has the same behavior as the bits in
Register Name:
Register Description:
Register Address:
Name
Default
Bit 5: Activity Alarm for Input Clock 4 (ACT4). This real-time status bit is set to 1 when the leaky bucket
accumulator for IC4 reaches the alarm threshold specified in the
the BUCKET field of ICR4). An activity alarm clears the IC4 status bit in the
clock. See section 7.5.2.
Bit 4: Phase Lock Alarm for Input Clock 4 (LOCK4). This status bit is set to 1 if IC4 is the selected reference and
the T0 DPLL cannot phase lock to IC4 within the duration specified in the
seconds). A phase lock alarm clears the IC4 status bit in VALSR1, invalidating the IC4 clock. If LKATO = 1 in
MCR3
System software can clear LOCK4 by writing 0 to it, but writing 1 is ignored. See section 7.7.1.
Bit 1: Activity Alarm for Input Clock 3 (ACT3). This bit has the same behavior as the ACT4 bit but for the IC3
input clock.
Bit 0: Phase Lock Alarm for Input Clock 3 (LOCK3). This bit has the same behavior as the LOCK4 bit but for the
IC3 input clock.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
then LOCK4 is automatically cleared after a time-out period of 128 seconds. LOCK4 is a read/write bit.
0 = Invalid
1 = Valid
MSR4
ISR
Bit 7
Bit 7
Bit 7
--
--
--
0
0
0
and section 7.7.1.6.
register). See also the
HORDY
Bit 6
Bit 6
Bit 6
--
--
0
0
0
VALSR1
Input Clock Valid Status Register 1
0Eh
VALSR2
Input Clock Valid Status Register 2
0Fh
ISR2
Input Status Register 2
11h
Preliminary. Subject to Change Without Notice.
ACT4
Bit 5
Bit 5
Bit 5
MSR1
IC6
--
0
0
1
register and section 7.5.
55 of 110
LOCK4
Bit 4
Bit 4
Bit 4
IC5
--
0
0
0
LBxU
Bit 3
Bit 3
Bit 3
IC4
--
0
0
--
0
register (where ‘x’ in ‘LBxU’ is specified in
VALSR1
Bit 2
Bit 2
Bit 2
IC3
PHLKTO
--
--
0
0
0
VALSR1
register, invalidating the IC4
register (default = 100
ACT3
but for the IC9 clock.
Bit 1
Bit 1
Bit 1
--
--
0
0
1
LOCK3
Bit 0
Bit 0
Bit 0
DS3105
IC9
--
0
0
0