DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 44

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

8
The DS3105 has an overall address range from 000h to 1FFh.
each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “--“ are reserved
and must be written with 0. Writing other values to these registers may put the device in a factory test mode
resulting in undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation. Register
fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are read-
write. Register fields are described in detail in the register descriptions that follow
8.1 Status Bits
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the
time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending
on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status
bits can cause an interrupt request on the INTREQ pin if enabled to do so by corresponding interrupt enable bits.
ISR#.LOCK# are special-case latched status bits because they cannot create an interrupt request on the INTREQ
pin and a “write 0” is needed to clear them.
8.2 Configuration Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “--“ are reserved and must be written with 0.
8.3 Multi-Register Fields
Multi-register fields—such as FREQ[18:0] in registers FREQ1,
ensure that the bytes of the field remain consistent. A write access to a multi-register field is accomplished by
writing all the registers of the field in any order, with no other accesses to the device in between. If the write
sequence is interrupted by another access, none of the bytes are written and the MSR4:MRAA latched status bit is
set to indicate the write was aborted. A read access from a multi-register field is accomplished by reading the
registers of the field in any order, with no other accesses to the device in between. When one register of a multi-
register field is read, the other register(s) in the field are frozen until after they are all read. If the read sequence is
interrupted by another access, the registers of the multi-byte field are unfrozen and the MSR4:MRAA bit is set to
indicate the read was aborted. For best results, interrupt servicing should be disabled in the microprocessor before
a multi-register access and then enabled again after the access is complete. The multi-register fields are:
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
REGISTER DESCRIPTIONS
Field
FREQ[18:0]
MCLKFREQ[15:0]
HARDLIM[9:0]
DIVN[15:0]
OFFSET[15:0]
PHASE[15:0]
FREQ1, FREQ2,
MCLK1,
DLIMIT1,
DIVN1,
OFFSET1,
PHASE1,
Registers
Preliminary. Subject to Change Without Notice.
DIVN2
MCLK2
DLIMIT2
PHASE2
OFFSET2
FREQ3
44 of 110
FREQ2
Table 8-1
Addresses
07, 0C, 0D
3C, 3D
41, 42
46, 47
70, 71
77, 78
and FREQ3—must be handled carefully to
in section
Type
read-only
read/write
read/write
read/write
read/write
read-only
Table
8.4
8-1.
shows the register map. In
DS3105