DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 28

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DS3105

Manufacturer Part Number
DS3105
Description
Line Card Timing IC
Manufacturer
Maxim Integrated Products
Datasheet

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The inactivity detector is enabled by setting NALOL=1 in the
DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See section 7.5.3.
When the T0 DPLL declares loss of phase lock, the state machine immediately transitions to the loss-of-lock state,
which sets the STATE bit in the
When the T4 DPLL declares loss of phase lock, the T4LOCK bit is cleared in the
T4LOCK bit in the
7.7.7 Phase Build-Out
7.7.7.1
When MCR10:PBOEN=0, phase build-out is not performed during reference switching. The T0 DPLL always locks
to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to the
next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients on
output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference.
When MCR10:PBOEN=1, phase build-out is performed during reference switching (or exiting from holdover). With
PBO enabled, if the selected reference fails and another valid reference is available then the device enters a
temporary holdover state in which the phase difference between the new reference and the output is measured
and fed into the DPLL loop to absorb the input phase difference. Similarly, during transitions from full-holdover,
mini-holdover or free-run to locked mode, the phase difference between the new reference and the output is
measured and fed into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the
input phase difference, the output phase transient is less than or equal to 5 ns.
Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ=1.
When PBO is frozen the T0 DPLL ignores subsequent phase build-out events and maintains the current phase
offset between inputs and outputs.
Disabling PBO while the T0 DPLL is not in the free-run or holdover states (locking or locked) will cause a phase
change on the output clocks while the DPLL switches to tracking the selected reference with 0 degrees of phase
error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO (which
includes un-freezing) while locking or locked also causes a PBO event.
7.7.7.2
An uncertainty of up to 5 ns is introduced each time a phase build-out event occurs. This uncertainty results in a
phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The
register specifies a small fixed offset for each phase build-out event to skew the average error toward zero and
eliminate accumulation of phase shifts in one direction.
7.7.8 Input to Output (Manual) Phase Adjustment
When phase build-out is disabled (PBOEN=0 in MCR10), the
the T0 DPLL output clocks with respect to the selected reference when locked. Output phase offset can be
adjusted over a ±200 ns range in 6 ps increments. This phase adjustment occurs in the feedback clock so that the
output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. Simply
writing to the
can be considered to be a delay adjustment. Changing the OFFSET adjustment while in free-run or holdover state
will not cause an output phase offset until it exits the state and enters one of the locking states.
7.7.9
When a phase buildout occurs, either automatic or manual, the feedback frequency synthesizer does not get an
internal alignment signal to keep it aligned with the output dividers, and therefore the phase difference between
input and output may become incorrect. Setting the FSCR3:RECAL bit periodically causes a recalibration process
to be executed which corrects any phase error that may have occurred.
During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to
zero, resets all clock dividers, ramps the phase offset to the value stored in the
switches the DPLL out of mini-holdover. If the
process will ramp the phase offset to the new offset value.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Phase Recalibration
Automatic Phase Build-Out in Response to Reference Switching
PBO Phase Offset Adjustment
OFFSET
MSR3
registers with phase build-out disabled causes a change in the input to output phase, which
register and requests an interrupt if enabled.
MSR2
Preliminary. Subject to Change Without Notice.
register and requests an interrupt if enabled.
OFFSET
28 of 110
registers are written during the recalibration process, the
OFFSET
PHLIM1
registers can be used to adjust the phase of
register. When this detector is enabled the
OPSTATE
OFFSET
register, which sets the
registers, and then
DS3105
PBOFF

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