DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 66

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Automatic Bandwidth Selection (AUTOBW). See section 7.7.3.
Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e. frozen)
when the DPLL reaches minimum or maximum frequency, as set by the HARDLIM field in
When the integral path is frozen, the current DPLL frequency in registers FREQ1,
frozen. Setting LIMINT=1 minimizes overshoot when the DPLL is pulling in. See section 7.7.3.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = Always selects locked bandwidth from the
1 = Automatically selects either locked bandwidth
0 = Don’t freeze integral path at min/max frequency
1 = Freeze integral path at min/max frequency
register) as appropriate
AUTOBW
Bit 7
1
Bit 6
--
1
MCR9
Master Configuration Register 9
3Bh
Preliminary. Subject to Change Without Notice.
Bit 5
--
1
66 of 110
Bit 4
T0LBW
--
1
(T0LBW
register
LIMINT
register) or acquisition bandwidth
Bit 3
1
Bit 2
--
0
FREQ2
DLIMIT1
Bit 1
and
--
1
FREQ3
(T0ABW
and DLIMIT2.
Bit 0
DS3105
--
1
is also