DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 20

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

7.6 Input Clock Priority, Selection and Switching
7.6.1
During normal operation, the selected reference for the T0 DPLL is chosen automatically based on the priority
rankings assigned to the input clocks in the input priority registers
has priority fields for one or two input clocks. When T4T0=0 in the
input clock priorities for the T0 DPLL. When T4T0=1, they have no meaning. The default input clock priorities are
shown in
There is an inter-lock mechanism between IC3 and IC5 and between IC4 and IC6 so that only two of the inputs can
be automatically selected. When IPR2.PRI3 is written with a priority other than 0, IPR3.PRI5 is automatically set to
0. When IPR3.PRI5 is written with a priority other than 0, IPR2.PRI3 is automatically set to 0. When IPR2.PRI4 is
written with a priority other than 0, IPR3.PRI6 is automatically set to 0. When IPR3.PRI6 is written with a priority
other than 0, IPR2.PRI4 is automatically set to 0.
Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable
for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks.
Table 7-3. Default Input Clock Priorities
7.6.2 Automatic Selection Algorithm
The real-time valid/invalid state of each input clock is maintained in the
selected reference can be marked invalid for phase lock, frequency or activity. Other input clocks can be
invalidated for frequency or activity.
The reference selection algorithm for the T0 DPLL chooses the highest-priority valid input clock to be the selected
reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table
of valid inputs. The top three entries in this table and the selected reference are displayed in the
PTAB2
the T0 DPLL. When T4T0=1, they have no meaning.
If two or more input clocks are given the same priority number then those inputs are prioritized among themselves
using a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid then the next
equal-priority clock in the list becomes the selected reference. If an equal-priority clock that is not the selected
reference becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is
inherently non-revertive, and revertive switching mode (see next paragraph) has no effect in the case where
multiple equal-priority inputs have the highest priority.
An important input to the selection algorithm for the T0 DPLL is the REVERT bit in the
mode (REVERT=1), if an input clock with a higher priority than the selected reference becomes valid, the higher-
priority reference immediately becomes the selected reference. In non-revertive mode (REVERT=0), the higher-
priority reference does not immediately become the selected reference but does become the highest-priority
reference in the priority table (REF1 field in the
highest-priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.)
For many applications, non-revertive mode is preferred for the T0 DPLL because it minimizes disturbances on the
output clocks due to reference switching.
In non-revertive mode, planned switchover to a newly-valid higher-priority input clock can be done manually under
software control. The validation of the new higher-priority clock sets the corresponding status bit in the
MSR2
respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive
the switchover to the higher-priority clock.
Input Clock
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register, which can drive an interrupt request on the INTREQ pin if needed. System software can then
IC3
IC4
IC5
IC6
IC9
registers. When T4T0=0 in the
Priority Configuration
Table
7-3.
Default Priority
T0 DPLL
0 (off)
0 (off)
2
3
5
Preliminary. Subject to Change Without Notice.
MCR11
register, these registers indicate the highest priority input clocks for
PTAB1
20 of 110
register). (The selection algorithm always switches to the
(IPR2
MCR11
,
IPR3
VALSR1
register, the IPR registers specify the
and IPR5). Each of these registers
and
MCR3
VALSR2
register. In revertive
registers. The
PTAB1
MSR1
DS3105
and
or