DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 68

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an unsigned integer that specifies the hard frequency limit or pull-in/hold-in range of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL=1 in the
frequency exceeds the hard limit then the DPLL declares loss-of-lock. The hard frequency limit in ppm is
±HARDLIM[9:0] * 0.0782. The default value is normally ±9.2 ppm. If external reference switching mode is enabled
during reset (see section 7.6.5), the default value is configured to ±79.794 ppm (3FFh). See section 7.7.6.
Register Name:
Register Description:
Register Address:
Name
Default
Bits 1 to 0: DPLL Hard Frequency Limit (HARDLIM[9:8]). See the
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Bit 7
Bit 7
--
0
0
Bit 6
Bit 6
--
1
0
DLIMIT1
DPLL Frequency Limit Register 1
41h
DLIMIT2
DPLL Frequency Limit Register 1
42h
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
--
1
0
68 of 110
Bit 4
Bit 4
--
1
0
HARDLIM[7:0]
Bit 3
Bit 3
--
0
0
DLIMIT1
register description.
Bit 2
Bit 2
--
1
0
DLIMIT3
Bit 1
Bit 1
register, if the DPLL
HARDLIM[9:8]
1
0
Bit 0
Bit 0
DS3105
0
0